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I will design digital ics from rtl to gdsii using cadence
I will design and debug Verilog SystemVerilog RTL modules and create testbenches
Hi, I'm Abdullah Tahir, a Computer Engineer specializing in Digital IC Design and RTL development. I work with Verilog, SystemVerilog, digital logic, simulation, and verification for FPGA and ASIC-ori...
Over deze dienst
Hi, I'm Abdullah, an IC Design professional specializing in digital IC implementation and physical design workflows.
What I Offer:
RTL & Synthesis: Review Verilog/SystemVerilog RTL, perform synthesis, and generate netlists and reports.
Physical Design: Floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and timing analysis.
ASIC Implementation: Block-level digital designs through the RTL-to-GDSII flow.
Analysis: Timing, area, congestion, and physical-design reports to identify implementation issues.
GDSII: Generate layout data for supported projects and technology flows.
Tools:
Cadence Genus
Cadence Innovus
Verilog / SystemVerilog
Digital IC / ASIC Design
I focus on organized implementation, clear documentation, and following your design specifications and constraints.
Please contact me before ordering large or full-chip projects so I can review the RTL, PDK/technology, constraints, and required deliverables.
Regards,
Abdullah Tahir
Veelgestelde vragen
Q1. What does your RTL-to-GDSII service include?
The flow can include RTL review, synthesis, floorplanning, power planning, placement, CTS, routing, timing analysis, physical verification, and GDSII generation depending on the selected package and project requirements.
Q2. Can you work with Verilog and SystemVerilog RTL?
Yes. I can review and prepare Verilog/SystemVerilog RTL for synthesis and digital IC implementation.
Q3. Which Cadence tools do you use?
I primarily work with Cadence Genus for synthesis and Cadence Innovus for digital physical design and implementation.
Q4. Can you perform RTL synthesis?
Yes. I can synthesize the provided RTL and analyze the generated netlist and synthesis reports.
Q5. Can you perform placement, CTS, and routing?
Yes. These physical-design stages are available in the Standard and Premium packages, subject to the project setup and technology flow.
Q7. Can you generate GDSII?
Yes, for supported projects where the required technology, libraries, PDK, and implementation flow are available.
Q9. Do you handle complete ASIC or full-chip projects?
I mainly work on block-level and small-to-medium digital IC projects. Please contact me first for large or full-chip designs so I can review the requirements.
