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I will design and debug systemverilog rtl modules and testbenches
I will design and debug Verilog SystemVerilog RTL modules and create testbenches
Hi, I'm Abdullah Tahir, a Computer Engineer specializing in Digital IC Design and RTL development. I work with Verilog, SystemVerilog, digital logic, simulation, and verification for FPGA and ASIC-ori...
Over deze dienst
Hi, I'm Abdullah, a Digital IC Design professional specializing in Verilog, SystemVerilog, and RTL development for digital design projects.
What I Offer:
RTL Module Design: Clean and synthesizable modules for your required functionality.
Digital Logic: FSMs, counters, registers, ALUs, multiplexers, datapaths, and control units.
Verification: Testbench development, simulation, waveform analysis, and functional testing.
Debugging: Identification and correction of issues in existing HDL source code.
ASIC & FPGA RTL: Designs suitable for academic, prototyping, and hardware-development workflows.
Why Choose Me:
I focus on clear, structured code that follows your specifications and is easy to understand and simulate. Testing is performed according to the selected package to help confirm the expected behavior.
You can provide a specification, block diagram, timing diagram, existing source code, or other project requirements.
Please contact me before ordering large or complex projects so I can review the scope and requirements.
Let's turn your digital design idea into a reliable hardware description.
Regards,
Abdullah Tahir
Veelgestelde vragen
Can you work with both Verilog and SystemVerilog?
Yes. I can develop or modify designs using either language according to your project requirements.
What types of digital circuits can you design?
I can work on FSMs, counters, registers, ALUs, datapaths, control units, multiplexers, encoders, decoders, FIFOs, and similar digital logic.
Can you create a testbench?
Yes. Testbench development and functional simulation are available in the Standard and Premium packages.
Can you debug existing HDL code?
Yes. Send your source files, error messages, simulation results, or waveform screenshots, and I can investigate the issue.
Will the code be synthesizable?
Yes. I focus on structured RTL suitable for synthesis, provided the project requirements and target technology are clearly defined.
Can you design Moore and Mealy FSMs?
Yes. I can implement both types, including sequence detectors and custom state-based control logic.
