Risico: vind de beste diensten

Risico: ontdek hier de beste freelance diensten voor een succesvolle afronding van je project.

109 beschikbare diensten

provide risc v assembly code

M

Niveau 1

I will provide risc v assembly code

4,8(5)

design and simulate customize risc v processor

M

Niveau 1

I will design and simulate customize risc v processor

5,0(2)

code in verilog and vhdl for dld, fpga and risc v

H

I will code in verilog and vhdl for dld, fpga and risc v

design risc v processors using verilog or system verilog

S

Niveau 1

I will design risc v processors using verilog or system verilog

5,0(6)

do mips,risc v and x86 assembly coding and debugging

T

I will do mips,risc v and x86 assembly coding and debugging

do computer architecture, organization ,risc v, mips and assembly language

A

I will do computer architecture, organization ,risc v, mips and assembly language

do risc v processor programming using verilog and sv

M

I will do risc v processor programming using verilog and sv

4,1(5)

do computer architecture, risc v, arm and all computer science related tasks

A

I will do computer architecture, risc v, arm and all computer science related tasks

5,0(1)

design risc v cpu and fpga rtl using verilog vhdl and scripting

R

Niveau 2

I will design risc v cpu and fpga rtl using verilog vhdl and scripting

4,0(1)

do computer architecture, organization, assembly language,mips and risc v

A

I will do computer architecture, organization, assembly language,mips and risc v

do risc v programming and projects in assembly, c, and fpga implementation

f

I will do risc v programming and projects in assembly, c, and fpga implementation

build advanced python automation ai ml systems and risc v tools

R

Niveau 2

I will build advanced python automation ai ml systems and risc v tools

develop bare metal firmware for arm cortex and risc v mcus

A

Niveau 2

I will develop bare metal firmware for arm cortex and risc v mcus

5,0(1)

do computer architecture, orginazation, assembly language,mips, risc v

R

I will do computer architecture, orginazation, assembly language,mips, risc v

do computer architecture, organization, operating system, x86, cpp, mips, risc v

E

I will do computer architecture, organization, operating system, x86, cpp, mips, risc v

assist with verilog vhdl dsp risc v fpga implementation using vivado quartus

U

I will assist with verilog vhdl dsp risc v fpga implementation using vivado quartus

5,0(1)

do computer architecture, operating system, assembly language ,mips and risc v

A

I will do computer architecture, operating system, assembly language ,mips and risc v

help you computer architecture, risc v, assembly language and operating syetem

S

I will help you computer architecture, risc v, assembly language and operating syetem

help computer architecture mips risc v assembly language and operating system

P

I will help computer architecture mips risc v assembly language and operating system

do operating system, computer science and organization, mips, risc v, lc3, linux

M

I will do operating system, computer science and organization, mips, risc v, lc3, linux

do computer architecture, assembly language, operating system, mips, risc v, lc3

Z

I will do computer architecture, assembly language, operating system, mips, risc v, lc3

do digital logic and fpga projects verilog vhdl dsp risc v vivado quartus

P

I will do digital logic and fpga projects verilog vhdl dsp risc v vivado quartus

do computer architecture assigned, processor design, system verilog, risc, tasks

A

I will do computer architecture assigned, processor design, system verilog, risc, tasks

riscv project design and verification, verilog, system verilog, assembly,fsm

A

Niveau 1

I will riscv project design and verification, verilog, system verilog, assembly,fsm

computer architecture, mips, x86, assembly language, riscv, operating system

K

I will computer architecture, mips, x86, assembly language, riscv, operating system

provide uvm based verification environment using system verilog

M

Niveau 1

I will provide uvm based verification environment using system verilog

do computer architecture ,operating system, arm , riscv and xv6

A

I will do computer architecture ,operating system, arm , riscv and xv6

do riscv programming and projects including assembly, c, and fpga solutions

R

Niveau 2

I will do riscv programming and projects including assembly, c, and fpga solutions

4,6(19)

build digital system design, computer architecture modules, and datapath

J

I will build digital system design, computer architecture modules, and datapath

5,0(1)

do computer science, c, cpp, riscv, mips, xv6, x86, assembly language and matlab

N

I will do computer science, c, cpp, riscv, mips, xv6, x86, assembly language and matlab

5,0(1)

do computer architecture, operating system, assembly language

p

I will do computer architecture, operating system, assembly language

do computer architecture, organization, operating system, mips, xv6 and riscv

A

I will do computer architecture, organization, operating system, mips, xv6 and riscv

help you with matlab, operating system and assembly language tasks

Z

I will help you with matlab, operating system and assembly language tasks

do uvm verification and verilog systemverilog rtl design

S

I will do uvm verification and verilog systemverilog rtl design

write, simulate and debug riscv assembly code and isa based designs

S

Niveau 1

I will write, simulate and debug riscv assembly code and isa based designs

do assigned computer architecture, riscv programming, assembly, fpga design task

M

I will do assigned computer architecture, riscv programming, assembly, fpga design task

design, debug, and optimize riscv digital systems using systemverilog and c

F

I will design, debug, and optimize riscv digital systems using systemverilog and c

micro led wearable iot device screens dashboard pcb firmware, esp32 nrf iot ble

E

I will micro led wearable iot device screens dashboard pcb firmware, esp32 nrf iot ble

do computer architecture mips rics v assembly language and operating system

S

I will do computer architecture mips rics v assembly language and operating system

provide customized fpga design and simulation

M

Niveau 1

I will provide customized fpga design and simulation

5,0(1)

do custom design digital circuits and processors in logisim

M

I will do custom design digital circuits and processors in logisim

4,7(7)

design custom fpga and rtl projects using verilog, systemverilog, and vivado

E

Engr.sana Ullah

Niveau 1

I will design custom fpga and rtl projects using verilog, systemverilog, and vivado

4,4(7)

do logisim, multisim and ltspice projects

P

I will do logisim, multisim and ltspice projects

5,0(5)

do dld, verilog, system verilog, c , riscv assembly, uvm, testbench, asic, gds

S

I will do dld, verilog, system verilog, c , riscv assembly, uvm, testbench, asic, gds

5,0(2)

do verilog, vhdl, system verilog rtl for fpga on vivado, quartus

L

Niveau 1

I will do verilog, vhdl, system verilog rtl for fpga on vivado, quartus

5,0(28)

do assembly language and operating systems projects

M

Niveau 1

I will do assembly language and operating systems projects

4,0(6)

do computer architecture and science , lc3, xv6, x86, mips, operating system

Z

I will do computer architecture and science , lc3, xv6, x86, mips, operating system

do riscv projects using verilog and system verilog

W

I will do riscv projects using verilog and system verilog

5,0(2)

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Risico: gerelateerde diensten

Architectuur Besturingssysteem Mips Verilog Montage Fpga Assembleertaal Riscv Organisatie Computertechnologie