h
harin_maniyar

Maniyar

@harin_maniyar
5,0(1)

ASIC verification

India
Gujarati, Engels, Hindi
Sommige informatie wordt in het Engels weergegeven.
Over mij
I have hands-on experience in a wide range of digital design and verification projects using Verilog HDL. My expertise spans across Digital Electronics, Verilog HDL, System Verilog, UVM methodologies. I have successfully delivered design and verification solutions across multiple projects and recently worked on Gate-Level Simulations (GLS), enhancing my understanding of timing, netlist-level behavior, and real-world implementation aspects.... Lees meer

Skills

h
harin_maniyar
Maniyar
offline • 

Bekijk mijn diensten

Programmering en technologie
I will help to design rtl in verilog
5,0(1)
VanafUS$ 5 / projectMeer informatie
Programmering en technologie
I will help verifying complex design by developing sv, uvm testbench
VanafUS$ 10 / projectMeer informatie

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