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hasnatsajid208

Hasnat S

@hasnatsajid208

RTL Design Verification Engineer

Pakistan
Engels, Urdu
Sommige informatie wordt in het Engels weergegeven.
Over mij
I am a digital design engineer with hands-on experience across full-custom RTL, verification, and FPGA integration. I specialize in architecture, self-checking testbenches, and timing closure for projects ranging from legacy system emulation to cryptographic accelerators. I am comfortable owning blocks end-to-end and optimizing for high-performance hardware.... Lees meer

Skills

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hasnatsajid208
Hasnat S
offline • 

Bekijk mijn diensten

Geïntegreerde systemen en IoT
I will design a custom uart, spi, or i2c interface in verilog or systemverilog
VanafUS$ 10 / projectMeer informatie
Geïntegreerde systemen en IoT
I will write systemverilog, verilog testbenches and verify your rtl design
VanafUS$ 10 / projectMeer informatie

Portfolio

Werkervaring

freelance

RTL Design & Verification Engineer

freelance • Freelance

Jan 2023 - Present • 3 yrs 9 mos

Digital design engineer providing services across full-custom RTL, verification, and FPGA integration. Responsibilities include cycle-accurate legacy system emulation, cryptographic accelerator design, and owning blocks end-to-end from architecture to timing closure. Experienced in self-checking testbenches, synthesis, and design reviews for short-term contracts and IP blocks.