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Muhammadans
@muhammadans643
Computer Engineer Digital Systems and FPGA Designer Machine Learning
Pakistan
Engels
Over mij
I’m a Computer Engineering graduate from UET with 4+ years of hands-on experience in Digital Logic Design, VLSI, ASIC, and FPGA development. I specialize in Verilog/VHDL and the complete Cadence RTL-to-GDSII flow, including RTL design, functional verification, synthesis, floorplanning, placement, CTS, routing, timing closure, and sign-off checks. I also work with MATLAB, C/C++, Python, and Machine Learning. I focus on delivering clean, optimized, and well-documented designs with clear communication, reliability, and on-time delivery.
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Muhammadans
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Bekijk mijn diensten
Geïntegreerde systemen en IoT
I will do verilog fpga rtl and digital system design projects
Geïntegreerde systemen en IoT
I will do analog ic design cmos layout and gdsii projects
