m
muhib_17

Muhib A

@muhib_17

Student

Bangladesh
Engels
Sommige informatie wordt in het Engels weergegeven.
Over mij
Hello! I am Muhib, an undergraduate student in Electronics and Communication Engineering with 3 years experience and expertise in Digital logic design , RTL design with Verilog HDL , Design Simulation.I also have expertise in using tools like Proteus, Logisim , Modelsim.I can assist you in designing , debugging and simulating digital circuits as well as hardware implementation using Verilog.... Lees meer

Skills

m
muhib_17
Muhib A
offline • 

Bekijk mijn diensten

Programmering en technologie
I will assist you with digital logic design tasks, lab works and assignments
Programmering en technologie
I will design debug and simulate verilog rtl projects for fpga

Portfolio