I will design verilog rtl for fpga, asic and vlsi projects

Need synthesizable Verilog/SystemVerilog RTL for an FPGA or ASIC project?

I am a PhD researcher in VLSI architecture with 5 years of industry experience developing safety-critical ADAS hardware at TCS. I transform specifications and algorithms into clean, modular, production-ready RTL optimized for synthesis, timing, and area.

All RTL is written from scratch and delivered with clear documentation, verification support, and modular coding practices.

️ Common Projects & Interfaces:

• Protocols: UART, SPI, I2C, I2S
• Interconnects: AXI4, AHB Interfaces
• Control Logic: Custom FSMs
• DSP: Filters (Gabor, FIR), Signal Processing
• Hardware AI: Neural Network Accelerators, CORDIC

️ Core Expertise:

• RTL Design: Verilog & SystemVerilog
• FPGA: Xilinx Vivado (Zynq/Artix), Intel Quartus
• ASIC Flow: Synthesizable RTL targeting strict timing-aware design
• Verification: Self-checking testbenches & waveform debugging (ModelSim/XSim)

Deliverables:

• Synthesizable Source Code
• Testbench & Simulation Results
• Microarchitecture Documentation

Message me before ordering to discuss specs and target devices!