I will architect custom verilog rtl for fpga and asic synthesis

Senior VLSI & FPGA Architect | 10 Yrs Expertise

Stop settling for RTL that only works in simulation. I deliver production-ready hardware and enterprise-grade VLSI implementation as a PhD-level architect who understands physical silicon constraints.

Areas of Proficiency:

• Digital Logic: Custom FSMs, Datapaths, Memory controllers.
• AI & DSP: Neural Network Accelerators, CORDIC, Gabor filters.
• ASIC Synthesis: Gate-level netlists, PPA optimization (<90nm).
• Physical Design: Floorplanning, CTS, PnR, Layout.
• FPGA Flow: Synthesis, bitstream, timing closure.
• Verification: Robust testbenches & waveform debugging.

Toolstack & Skills:

• ASIC: Cadence Genus, Innovus, Virtuoso.
• FPGA: Xilinx Vivado, Intel Quartus Prime.
• HDL/Sim: Verilog, SystemVerilog, VHDL, ModelSim.
• Open-Source: OpenLane, Magic, Xschem, Netgen.

Why Choose Me:

• PhD-Level: I translate complex NN and algorithms into physical silicon.
• Enterprise Reliability: 5 yrs designing safety-critical ADAS.

NB: Message me before ordering to discuss your architecture and tech nodes!

• #Verilog #FPGA #ASIC #SystemVerilog #Cadence