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Syed Anees
@syedanees089
Verilog VHDL and FPGA Technical Writer Engineering Documentation Specialist
Pakistan
Engels, Urdu
Over mij
I am a final year Computer Engineering student at UET Taxila, graduating June 2026, with expertise in Verilog, VHDL, FPGA design, and digital logic systems. I combine technical knowledge with strong English writing skills to deliver clear, professional documentation for hardware and digital design projects.
Need lab reports, project documentation, or FYP write-ups? I deliver work that is technically accurate and professionally written.
Most technical writers don’t understand your circuit. Most engineers can’t write clearly. I do both.
Skills
Syed Anees
offline •
Bekijk mijn diensten
Technische teksten
I will write verilog vhdl and fpga project documentation
